Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a ringback circuit for a semiconductor memory device.
A semiconductor memory device including DRAM may receive write data from a chip set (memory controller). Here, both of the semiconductor memory device and the chip set are synchronized and operated by a system clock signal. When data is transferred to the semiconductor memory device from the chip set, the load on and trace of the data signal are different from those of the system clock signal, and a skew (e.g., a phase difference) occurs between the data and the system clock signal due to spatial differences in transferring the system clock signal to a plurality of memories.
In order to reduce the skew between the data and the system clock signal, a data strobe signal DQS is transferred together when the data is transferred to the semiconductor memory device. The data strobe signal DQS is called an echo clock signal, and has the same load and trace as the data. Therefore, when the semiconductor memory device strobes the data by using the data strobe signal DQS, the skew between the system clock signal and the data may be minimized.
Here, the data strobe signal DQS may toggle, for example, only in a predetermined period. When the toggling data strobe signal DQS returns to a high impedance (Hi-Z) state after a final clock edge, ringing often occurs. Such a phenomenon is referred to as write post-amble ringing. In other words, after the toggling of the data strobe signal DQS ends, a glitch occurs in the data strobe signal DQS due to noise. The write post-amble ringing may occur due to the characteristic of a transfer line during the transferring process of the data strobe signal or the characteristic of a buffer for interfacing the data strobe signal.
In order to prevent the write post-amble ringing, the semiconductor memory device includes a ringback circuit.
FIG. 1 is a block configuration diagram illustrating a ringback circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the ringback circuit 100 includes a filtering signal generation unit 110 and a data strobe signal filtering unit 120.
The filtering signal generation unit 110 is configured to receive a clock signal CLK and a write delay signal CASWL_15 obtained by delaying a write command by a desired period and generate a filtering signal DISDSP2D for filtering a data strobe signal DQS, The write command is not illustrated in FIG. 1. The strobe signal filtering unit 120 is configured to limit the toggling period of a data strobe falling pulse DQSFP2D in response to the filtering signal DISDSP2D. Here, the data strobe falling pulse DQSFP2D is a signal which is derived from the data strobe signal DQS and pulses in correspondence to a falling edge of the data strobe signal DQS.
FIG. 2 is an internal circuit diagram of the filtering signal generation unit 110 of FIG. 1.
Referring to FIG. 2, the filtering signal generation unit 110 includes a clock synchronization signal generation section 112 and a filtering signal output section 114. The clock synchronization signal generation section 112 is configured to synchronize the write delay signal CASWL_15 with the clock signal CLK and sequentially generate first to fourth rising edge synchronization signals RD1D<1> to RD1D<4> and first to third falling edge synchronization signals RD05D<2> to RD05D<4>. The filtering signal output section 114 is configured to logically combine the first to fourth rising edge synchronization edge signals RD1D<1> to RD1D<4>, the first to third falling edge synchronization signals RD05D<2> to RD05D<4>, and the write delay signal CASWL_15 and output the filtering signal DISDSP2D.
The clock synchronization signal generation section 112 includes first to fourth D flip-flops DFF1 to DFF4 configured to synchronize the respective input signals with the clock signal CLK.
The filtering signal output section 114 includes a first NAND gate NAND1, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a second NAND gate NAND2, and a first inverter INV1. The first NAND gate NAND1 is configured to receive the first to third falling edge synchronization signals RD05D<2> to RD05D<4> and perform a NAND operation on the received signals. The first NOR gate NOR1 is configured to receive an output signal INTO of the first NAND gate NAND1 and the write delay signal CASWL_15 and perform a NOR operation on the received signals. The second NOR gate NOR2 is configured to receive the first and second rising edge synchronization signals RD1D<1> and RD1D<2> and perform a NOR operation on the received signals. The third NOR gate NOR3 is configured to receive the third and fourth rising edge synchronization signals RD1D<3> and RD1D<4> and perform a NOR operation on the received signals. The second NAND gate NAND2 is configured to receive output signals INT1 to INT3 of the first to third NOR gates NOR1 to NOR3 and perform a NAND operation on the received signals. The first inverter INV1 is configured to invert an output signal INT4 of the second NAND gate NAND2 and output the filtering signal DISDSP2D.
Hereafter, the operation of the ringback circuit 100 of the conventional semiconductor memory device will be described with reference to FIG. 3.
FIG. 3 is a timing diagram explaining the operation of the ringback circuit of the conventional semiconductor memory device of FIG. 1.
In FIG. 3, the data strobe signal DQS includes a pre-amble period P in which the data strobe signal DQS previously starts toggling from a desired time point in a high impedance (Hi-Z) state, a period D for substantially outputting data after the preamble period P, and a post-amble period in which the data strobe signal DQS returns to the high-impedance state. Here, it can be seen that a glitch occurs in the data strobe signal DQS, when the toggling data strobe signal DQS returns to the high impedance state after a final falling edge, that is, during the post-amble period. Such a glitch which may cause a fail during the data output, may be filtered out. The filtering method will be described below.
First, the filtering signal generation unit 110 generates a filtering signal DISDSP2D for filtering a data strobe falling pulse DQSFP2D corresponding to a falling edge of the data strobe signal DQS. The filtering signal DISDSP2D is a signal for filtering the entire period of the data strobe signal DQS excluding the period D required for data output, and has a pulse width corresponding to the period D required for data output in the data strobe signal DQS.
In response to the filtering signal DISDSP2D, the data strobe signal filtering unit 120 filters the data strobe falling pulse DQSFP2D and outputs the filtered data strobe signal DQSFP4. If the data strobe falling pulse DQSFP2D is used without being filtered, undesired data is outputted by a final rising edge of the data strobe falling pulse DQSFP2D, that is, a pulse corresponding to a glitch occurring in the data strobe signal DQS.
According to the ringback circuit 100 of the semiconductor memory device, a fail caused by a glitch occurring in the data strobe signal DQS, when data is outputted, may be substantially prevented.
However, the ringback circuit 100 of the conventional semiconductor memory device also has the following features.
The filtering signal DISDSP2D for filtering the data strobe signal DQS is generated in the clock signal domain. That is, the filtering signal DISDSP2D is generated by a combination of the first to fourth rising edge synchronization signals RD1D<1> to RD1D<4> in synchronism with the clock signal CLK and the first to third falling edge synchronization signals RD05D<2> to RD05D<4>. Here, since the domain of the clock signal CLK is different from the domain of the data strobe signal DQS, a skew (e.g., a phase difference or misalignment of clock edges compared to edges of the data strobe signal DQS) may occur between the filtering signal DISDSP2D generated in the clock signal domain and the data strobe falling pulse DQSFP2D generated in the data strobe signal domain. In this case, since the data strobe falling pulse DQSFP2D may not be accurately filtered, a post-amble ringing may occur.
Here, a domain crossing margin tDQSS between the data strobe signal DQS and the clock signal CLK is often specified in specifications. Semiconductor memory devices are to support the pre-amble period of the data strobe signal DQS in a high-speed operation, where the pre-amble period of the data strobe signal DQS is variously supported and to accommodate the variously supported pre-amble periods of the data strobe signal DQS, various domain crossing margins tDQSS are used. Therefore, since the domain crossing margin tDQSS between the data strobe signal DQS and the clock signal CLK should satisfy the specification, the domain crossing margin tDQSS between the filtering signal DISDSP2D and the data strobe signal DQS is also limited. A ringback circuit which supports various preamble period schemes for the data strobe signal DQS is useful.